1. Technical Field
The present disclosure relates to a signal processing circuit.
2. Description of the Related Art
An AD converter accommodated to daisy chain connection has been put into practical use. Such a converter is described in the following literature, for example. Texas Instruments Incorporated, 24-Bit, Wide Bandwidth Analog-to-Digital Converter ADS1271 Data sheet Rev.B, November 2004—Revised October 2007, p.24, Search on Aug. 18, 2015, Internet (URL:http://www.tij.co.jp/jp/lit/ds/symlink/ads1271.pdf)
FIG. 7 illustrates a signal processing circuit 500 including daisy chain-connected AD converters. In the signal processing circuit 500, it is assumed that each AD converter is required to perform digital conversion at the same timing.
In the example of FIG. 7, three AD converters (first ADC, second ADC, and third ADC) are daisy chain-connected. An MPU retrieves serial digital data. Due to daisy chain connection, it is possible to simplify serial interface for digitally converting several analog data to retrieve as serial data.
Each ADC includes an analog input terminal (AINP), a digital output terminal (DOUT), a digital input terminal (DIN), a synchronizing signal input terminal (SYNC), a serial clock input terminal (SCLK), and a data ready output terminal (DRDY).
An MPU includes a digital input terminal (DIN), a serial clock output terminal (SCLK), a data ready input terminal (DRDY), a general-purpose input output terminal (GPIO), and a synchronizing signal output terminal (SYNC).
Each ADC becomes a reset state when a negative pulse is applied to the synchronizing signal input terminal (SYNC). In the example of FIG. 7, a synchronizing signal pulse is output from the synchronizing signal output terminal (SYNC) of the MPU. The synchronizing signal pulse is concurrently applied to the synchronizing signal input terminal (SYNC) of each ADC. Each ADC is simultaneously reset when the MPU outputs a synchronizing signal pulse after the power is turned on. Accordingly, conversion of each ADC is synchronized.
Thereafter, each ADC converts analog data input to each analog input terminal (AINP) to digital data at the same timing. Moreover, each ADC shifts out conversion data (digital data) from the digital output terminal (DOUT) at a falling edge of the SCLK. SCLK is output from the serial clock output terminal (SCLK) of the MPU. SCLK is concurrently input to the serial clock input terminal (SCLK) of each ADC.
The daisy chain-connected ADCs shift in digital data from the digital input terminal (DIN) at a falling edge of the SCLK. The data that has been shifted in is shifted out from the digital output terminal (DOUT) after the conversion data is shifted out.
In the example of FIG. 7, the digital output terminal (DOUT) of the first ADC is connected to the digital input terminal (DIN) of the MPU. The digital output terminal (DOUT) of the second ADC is connected to the digital input terminal (DIN) of the first ADC. The digital output terminal (DOUT) of the third ADC is connected to the digital input terminal (DIN) of the second ADC. The digital input terminal (DIN) of the third ADC is grounded.
The ADC sets the data ready output terminal (DRDY) as low level when it is data-ready for reading (that is, when it is ready to read data). Only the data ready output terminal (DRDY) of the first ADC is connected to the data ready input terminal (DRDY) of the MPU.
FIG. 8 is a timing chart for describing an operation of the signal processing circuit 500. As shown in FIG. 8, each ADC is simultaneously reset when a pulse is concurrently applied to the synchronizing signal input terminal (SYNC) at a time t1. Each ADC performs digital conversion at the same timing and outputs a DRDY signal at a time t2 after a predetermined period T1. The MPU only receives a DRDY signal output from the first ADC.
The MPU outputs SCLK to each ADC when the MPU receives a DRDY signal. Each ADC shifts out digital data at an edge of the SCLK. Due to daisy chain connection, the MPU sequentially acquires output data of the first ADC (ADC 1 data), output data of the second ADC (ADC 2 data), and output data of the third ADC (ADC 3 data) from the digital output terminal (DOUT) of the first ADC.
Subsequently, each ADC performs digital conversion at the same timing to output a DRDY signal for each predetermined period T2. Each ADC shifts out digital data at an edge of the SCLK output from the MPU in accordance with the DRDY signal. Each ADC repeats the above process.